Naoki FUJIEDA, Dr. Eng.

Publications

NOTE: Japanese publications are excluded from this page. The list of my works including Japanese is available in Japanese page or Google Scholar.

Journal

• Naoki Fujieda, Shuichi Ichikawa, Ryusei Oya, and Hitomi Kishibe: Design and implementation of an on-line quality control system for latch-based true random number generator, IEICE Transactions on Information and Systems, Vol. E106-D, No. 12, pp. 1940-1950 (12/2023). [DOI: 10.1587/transinf.2023PAP0001 (open access)]
• Shunsuke Matsuoka, Shuichi Ichikawa, and Naoki Fujieda: A True Random Number Generator That Utilizes Thermal Noise in a Programmable System-on-chip (PSoC), International Journal of Circuit Theory and Applications, Vol. 49, No. 10, pp. 3354–3367 (10/2021). [DOI: 10.1002/cta.3046] [view online via Wiley Sharing Link]
• Naoki Fujieda and Sogo Takashima: An MMCM-based high-speed true random number generator for Xilinx FPGA, International Journal of Networking and Computing, Vol. 11, No. 2, pp. 154–171 (07/2021). [abstract and pdf from IJNC (open access)]
• Naoki Fujieda, Masaaki Takeda, and Shuichi Ichikawa: An Analysis of DCM-based True Random Number Generator, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 67, No. 6, pp. 1109–1113 (06/2020). [DOI: 10.1109/TCSII.2019.2926555] [postprint]
• Naoki Fujieda, Kiyohiro Sato, Ryodai Iwamoto, and Shuichi Ichikawa: Evaluation of Register Number Abstraction for Enhanced Instruction Register Files, IEICE Transactions on Information and Systems, Vol. E101-D, No. 6, pp. 1521-1531 (06/2018). [DOI: 10.1587/transinf.2017EDP7221 (open access)]
• Naoki Fujieda and Shuichi Ichikawa: A Latch-latch Composition of Metastability-based True Random Number Generator for Xilinx FPGAs, IEICE Electronics Express, Vol. 15, No. 10, pp. 20180386:1-20180386:12 (05/2018). [DOI: 10.1587/elex.15.20180386 (open access)]
• Naoki Fujieda, Takumi Shinohara, Shuichi Ichikawa, Yuhki Sakaguchi, Shunsuke Matsuoka, and Hideki Kawaguchi: Attenuation Model for Error Correction of Ultrasonic Positioning System, IEEJ Journal of Industry Applications, Vol. 7, No. 2, pp. 181-188 (03/2018). [DOI: 10.1541/ieejjia.7.181 (open access)]
• Naoki Fujieda, Ryo Yamauchi, Hiroki Fujita, and Shuichi Ichikawa: A Virtual Cache for Overlapped Memory Accesses of Path ORAM, International Journal of Networking and Computing, Vol. 7, No. 2, pp. 106-123 (07/2017). [abstract and pdf from IJNC (open access)]
• Naoki Fujieda, Tasuku Tanaka, and Shuichi Ichikawa: Design and Implementation of Instruction Indirection for Embedded Software Obfuscation, Microprocessors and Microsystems, Vol. 45, Part A, pp.115–128 (08/2016). [DOI: 10.1016/j.micpro.2016.04.005] [postprint]
• Naoki Fujieda and Shuichi Ichikawa, An XOR-based Parameterization for Instruction Register Files, IEEJ Transactions on Electrical and Electronic Engineering, Vol. 10, No. 5, pp. 592–602 (09/2015). [DOI: 10.1002/tee.22123] [postprint]
• Shimpei Sato, Naoki Fujieda, Akira Moriya, and Kenji Kise: SimCell: A Processor Simulator for Multi-Core Architecture Research, IPSJ Transactions on Advanced Computing Systems, Vol.2, No.1, pp. 146–157 (03/2009). [DOI: 10.2197/ipsjtrans.2.81 (open access)]

Conference (Refereed, Oral/Video Presentation)

• Naoki Fujieda and Naoya Ito: A case for edge video processing with FPGA SoC: reversi board detection using Hough transform, 12th International Workshop on Computer Systems and Architectures (CSA-12) held in conjunction with CANDAR '24, pp. 50-55 (11/2024). [DOI: TBA]
• Naoki Fujieda and Atsuki Okuchi: A Novel Remote FPGA Lab Platform Using MCU-based Controller Board, 12th International Conference on Teaching, Assessment and Learning for Engineering (TALE 2023), pp. 188-193 (11/2023). [DOI: 10.1109/TALE56641.2023.10398409] [postprint]
• Ryusei Oya, Naoki Fujieda, and Shuichi Ichikawa: An HLS implementation of on-the-fly randomness test for TRNGs, 10th International Symposium on Computing and Networking (CANDAR 2022), pp. 151–157 (11/2022). [DOI: 10.1109/CANDAR57322.2022.00028] [postprint]
• Naoki Fujieda: A Python-based evaluation framework for stochastic computing circuits on FPGA SoC, 9th International Workshop on Computer Systems and Architectures (CSA-9) held in conjunction with CANDAR '21, pp. 81–86 (11/2021). [DOI: 10.1109/CANDARW53999.2021.00021] [Source code on GitHub] [postprint]
• Naoki Fujieda and Sogo Takashima: Enhanced use of mixed-mode clock manager for coherent sampling-based true random number generator, 12th International Workshop on Parallel and Distributed Algorithms and Applications (PDAA-12) held in conjunction with CANDAR '20, pp. 197–203 (11/2020). [DOI: 10.1109/CANDARW51189.2020.00047] [postprint]
• Naoki Fujieda: On the feasibility of TERO-based true random number generator on Xilinx FPGAs, 30th International Conference on Field-Programmable Logic and Applications (FPL 2020), pp. 103–108 (08/2020). [DOI: 10.1109/FPL50879.2020.00027] [postprint] [Source code on GitHub]
• Naoki Fujieda, Hitomi Kishibe, and Shuichi Ichikawa: A light-weight implementation of latch-based true random number generator, 15th International Wireless Communication and Mobile Computing Conference (IWCMC 2019), pp. 901-906 (06/2019). [DOI: 10.1109/IWCMC.2019.8766516] [postprint]
• Naoki Fujieda, Yusuke Ayuzawa, Masato Hongo, and Shuichi Ichikawa: A Multiple Clock Domain Design of High-radix Montgomery Multiplication for Simplicity, 2018 IEEE Region 10 International Conference (TENCON2018), pp. 1489-1492 (10/2018). [DOI: 10.1109/TENCON.2018.8650219] [postprint]
• Naoki Fujieda, Shuichi Ichikawa, Yoshiki Ishigaki, and Tasuku Tanaka: Evaluation of the hardwired sequence control system generated by high-level synthesis, 2017 IEEE International Symposium on Industrial Electronics (ISIE 2017), pp. 1261–1267 (06/2017). [DOI: 10.1109/ISIE.2017.8001426] [postprint]
• Naoki Fujieda, Ryo Yamauchi, and Shuichi Ichikawa: Last Path Caching: A Simple Way to Remove Redundant Memory Accesses of Path ORAM, 4th Workshop on Computer Systems and Architectures (CSA-4) held in conjunction with CANDAR '16, pp. 347–353 (11/2016). [DOI: 10.1109/CANDAR.2016.0068] [postprint]
• Naoki Fujieda, Kiyohiro Sato, and Shuichi Ichikawa: A complement to Enhanced Instruction Register File against Embedded Software Falsification, 5th Program Protection and Reverse Engineering Workshop (PPREW-5), No. 3 (12/2015). [DOI: 10.1145/2843859.2843864] [pdf available via ACM Author-Izer]
• Shunsuke Matsuoka, Naoki Fujieda, and Shuichi Ichikawa: S-Box Absorption Design for Key-Specific AES circuits, International Conference of Global Network for Innovative Technology (IGNITE2014), pp. 316–319 (12/2014).
• Yusuke Ayuzawa, Naoki Fujieda, and Shuichi Ichikawa: Design Trade-offs in SHA-3 Multi-Message Hashing on FPGAs, 2014 IEEE Region 10 International Conference (TENCON2014), No. 99 (10/2014). [DOI: 10.1109/TENCON.2014.7022311]
• Naoki Fujieda and Shuichi Ichikawa: Enhanced Instruction Register Files for Embedded Software Obfuscation, 29th International Conference on Computers and Their Applications (CATA-2014), pp. 153–158 (03/2014). [ISBN: 978-1-880843-95-6] [preprint]
• Naoki Fujieda and Shuichi Ichikawa: An XOR-based approach to merging entries for instruction register files, First Workshop on Computer Systems and Architectures (CSA-1) held in conjunction with CANDAR'13, pp. 332–337 (12/2013). [DOI: 10.1109/CANDAR.2013.60] [postprint]
• Takakazu Ikeda, Shinya Takamaeda-Yamazaki, Naoki Fujieda, Shimpei Sato,and Kenji Kise: Request Density Aware Fair Memory Scheduling, 3rd JILP Workshop on Computer Architecture Competitions (JWAC-3) in conjunction with ISCA-2012 (06/2012). [pdf available on the contest site]
• Shinya Takamaeda, Shintaro Sano, Yoshito Sakaguchi, Naoki Fujieda, and Kenji Kise: ScalableCore System: A Scalable Many-core Simulator by Employing Over 100 FPGA, 8th International Symposium on Applied Reconfigurable Computing (ARC2011), pp. 138–150 (03/2012). [DOI: 10.1007/978-3-642-28365-9_12]
• Naoki Fujieda and Kenji Kise: A Partitioning Method of Cooperative Caching with Hit Frequency Counters for Many-Core Processors, Third Workshop on Ultra Performance and Dependable Acceleration Systems (UPDAS-3) held in conjunction with ICNC'11, pp. 160–165 (12/2011). [DOI: 10.1109/ICNC.2011.31]
• Mochamad Asri, Naoki Fujieda, and Kenji Kise: Rethinking Processor Instruction Fetch: Inefficiencies-Cracking Mechanism, 2011 International SoC Design Conference (ISOCC2011), pp. 207–210 (11/2011). [DOI: 10.1109/ISOCC.2011.6138746]
• Naoki Fujieda, Takefumi Miyoshi, and Kenji Kise: SimMips: A MIPS System Simulator, Workshop on Computer Architecture Education(WCAE) held in conjunction with MICRO-42, pp. 32–39 (12/2009). [pdf available on the conference site]
• Yuhta Wakasugi, Naoki Fujieda, Shinya Takamaeda, and Kenji Kise: MipsCoreDuo: A Multifunction Dual-core Processor, International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS2009), pp.587–590 (01/2009). [DOI: 10.1109/ISPACS.2009.5383772]
• Shimpei Sato, Naoki Fujieda, Akira Moriya, and Kenji Kise: Processor Simulator SimCell to Accelerate Research on Many-core Processor Architectures, Workshop on Cell Systems and Applications (WCSA 2008) held in conjunction with ISCA-2008, Beijing, China, pp. 119–127 (06/2008).

Poster (Refereed)

• Hiroki Fujita, Naoki Fujieda, and Shuichi Ichikawa: An Analysis on Randomness of Path ORAM for Light-weight Implementation, 6th Workshop on Computer Systems and Architectures (CSA-6) held in conjunction with CANDAR '18, pp. 163–165 (11/2018). [DOI: 10.1109/CANDARW.2018.00037]
• Yoshiki Ishigaki, Naoki Fujieda, Yuumi Matsuoka, Kazuki Uyama, and Shuichi Ichikawa: An Obfuscated Hardwired Sequence Control Systm Generated by High Level Synthesis, 5th Workshop on Computer Systems and Architectures (CSA-5) held in conjunction with CANDAR '17, pp. 323–325 (11/2017). [DOI: 10.1109/CANDAR.2017.29]

Poster (Non-refereed)

• Shinya Takamaeda, Shimpei Watanabe, Shimpei Sato, Koh Uehara, Yuhta Wakasugi, Naoki Fujieda, Yosuke Mori, and Kenji Kise: ScalableCore : High-Speed Prototyping System for Many-Core Processors, in International Symposium on Low-Power and High-Speed Chips (COOL Chips), p. 161 (04/2009).

Dissertation

• Naoki Fujieda: Research on Many-core Cooperative Caching, Doctoral Thesis, Graduate School of Information Science and Engineering, Tokyo Institute of Technology (02/2013). [pdf available at Arch Lab.]
• selected as IPSJ Nominated Doctoral Thesis (SIGARC).

Award

• Ryusei Oya, Naoki Fujieda, and Shuichi Ichikawa: Outstanding Paper Award, "An HLS implementation of on-the-fly randomness test for TRNGs," 10th International Symposium on Computing and Networking (CANDAR 2022) (11/2022).
• Naoki Fujieda, 2019 Technologies Outstanding Reviewer Award, MDPI Technologies (01/2020).
• Naoki Fujieda and Shuichi Ichikawa: Best Paper Award Finalist, "Enhanced Instruction Register Files for Embedded Software Obfuscation," 29th International Conference on Computers and Their Applications (CATA-2014) (03/2014).
• Takakazu Ikeda, Shinya Takamaeda-Yamazaki, Naoki Fujieda, Shimpei Sato,and Kenji Kise: Performance Track Award, "Request Density Aware Fair Memory Scheduling," 3rd JILP Workshop on Computer Architecture Competitions (JWAC-3) in conjunction with ISCA-2012 (06/2012).

Research Grant

External Fund

• [2022 - 2024] The Nitto Foundation, "Application of FPGA Technology for Ultra Low-cost Image Processing" (1,000,000 JPY).
• [2021 - 2022] Entrusted research (shared), New Energy and Industrial Technology Development Organization (1,783,000 JPY).
• [2021 - 2023] JSPS KAKENHI Grant-in-Aid for Scientific Research (C) (Project No. 21K12164) "Research on "Touchable" Remote Learning System of Digital Circuit" (3,250,000 JPY).
• [2020] NAGAI Foundation for Science & Technology, "Research on FPGA Technology for Ultra Low-cost Image Processing" (1,000,000 JPY).
• [2017] Telecommunications Advancement Foundation, "Utilization of Large-scale Instruction Register Files for Concealment of Embedded Software" (740,000 JPY).
• [2014 - 2016] JSPS KAKENHI Grant-in-Aid for Encouragement of Young Scientists (B) (Project No. 26870278) "Research on Hardware Implementation Methodology of PLC Programs for Concealment and Obfuscation" (2,340,000 JPY).

Competitive Fund within Organization

• Aichi Institute of Technology
• [2019] Special Grant for Education and Research (Research C) "Extension of GGFront, Convenient and Portable Tool for VHDL Simulation" (496,000 JPY).
Toyohashi University of Technology
• [2018] Grant for Vitalization of Education and Research (Young Researchers) "Elemental Technologies towards Efficient Development of Custom Computing Systems with Instruction Set Simulator" (891,000 JPY).
• [2018] Grant for Support of Research Publication (3 Articles, 221,000 JPY in total).
• [2013] Grant for Vitalization of Education and Research (Young Researchers) "Research on Processor Technology enhancing Tamper Resistance of Embedded Systems" (992,000 JPY).

Society Activity

• Information Processing Society of Japan (IPSJ)
• [2021 – cont.] Senior Reviewer, IPSJ Journal.
• [2015 – 2021] Reviewer, IPSJ Journal.
• [2017 – 2021] Editorial Board Member, IPSJ Transactions on Advanced Computeing Systems (ACS).
• [2015 – 2019] Committee Member, IPSJ Special Interest Group on System Architecture (SIGARC).
• Institute of Electronics, Information, and Communication Engineers (IEICE)
• [2019 – cont.] Committee Member, IEICE Technical Committee on Computer Systems (CPSY).
• International Conference
• [2024] General Chair, 2nd Workshop on FPGA Technologies for Adaptive Computing (FTAC-2024), held in conjunction with 38th International Conference on Supercomputing (ICS 2024).
• [2021] Program Chair, Special Session on FPGA Technologies for Adaptive Computing (FTAC-2021), IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC).
• [2017 – cont.] Program Committee Member, International Symposium on Computing and Networking (CANDAR).
• [2015 – 2019] Program Committee Member, International Workshop on Computer Systems and Architectures (CSA).
• [2013 – cont.] Program Committee Member, International Workshop on Advances in Networking and Computing (WANC). [2024]
• Domestic Conference
• [2024 – cont.] Program Committee Member, Cross-disciplinary Workshop on Computing Systems, Infrastructures, and Programming (xSIG).
• [2017 – 2019] Program Committee Secretary, Cross-disciplinary Workshop on Computing Systems, Infrastructures, and Programming (xSIG).

Lecture

Full-term lecture and experiment

• Electronics and Information Networks major, Department of Electrical and Electronics Engineering, Faculty of Engineering, Aichi Institute of Technology
• [2019 – cont.] Experiment for Electronics and Information Networks 2
• [2019 – cont.] Computer Engineering
• [2019 – cont.] Digital Circuits 1
• [2017 – cont.] Digital Circuits 2
• [2017] Computer Systems 2
• Electrical and Electronics Engineering Course, Graduate School of Engineering, Aichi Institute of Technology
• [2020 – cont.] Advanced Digital Logic Design (conducted every other year)
• Department of Mechanical Engineering, National Institute of Technology, Toyota College
• [2025 – cont.] Electrical and Electronic Circuits B
• [2020 – 2023] Elementary Electrical and Electronic Circuits B
• Undergraduate Course of Electrical and Electronic Information Engineering, Toyohashi University of Technology
• Experimental Practice for Electrical, Electronic and Information Engineering 1
• [2013 – 2018] Logic Circuits I (Combinational Circuits)
• [2013 – 2018] Logic Circuits II (Sequential Circuits)
• [2013, 2015 – 2018] Introduction to Computer Organization
• [2013] Operational Amplifier Circuits for Linear Computation
• Experimental Practice for Electrical, Electronic and Information Engineering 2
• [2013 – 2018] Logic Circuits for Embedded Systems
• Leading the renewal of the theme in 2014
• [2014 – 2018] Control Programming for Microcomputers
• [2013] AD/DA Conversion and PCM Communication

Special lecture

• Challenges for Easy-to-learn Learning Environments of Digital Design, School of Electronic Science & Engineering, Southeast University, China (10/2024).