Profile: Naoki FUJIEDA

Updated on: February 1, 2024 (EN/JA)

A conference paper describing our remote FPGA lab platform, which was presented at TALE 2023, is now available at IEEE Xplore. The accepted version is also available on this site (Feb. 1, 2024).
A paper that describes an on-line quality control system of true random number generator, which was developed as a joint research with Custom Computing Systems Lab, TUT, has been published（Dec. 6, 2023）．
The accepted version of my FPL paper has also been available on this site (Oct. 16, 2020).
Source code of some of our project, including TC-TERO presented at FPL 2020, is now avaliable at GitHub (Aug. 26, 2020).

Associate Professor, Department of Electrical and Electronics Engineering, Faculty of Engineering, Aichi Institute of Technology

03/2008: Received BE from Tokyo Institute of Technology, Japan
02/2009: Established MieruPC Inc. based on the research achievement in Kise Laboratory, Tokyo Institute of Technology
03/2010: Received ME from Tokyo Institute of Technology, Japan
03/2011: Retired from MieruPC Inc. at the expiration of the term as the President/CEO
03/2013: Received DE from Tokyo Institute of Technology, Japan
04/2013 - 03/2019: Assistant Professor, Department of Electrical and Electronic Information Engineering, Toyohashi University of Technology
04/2017 - 03/2019: Part-time Lecturer, Department of Electrical and Electronics Engineering, Faculty of Engineering, Aichi Institute of Technology
04/2019 - 03/2021: Lecturer, Department of Electrical and Electronics Engineering, Faculty of Engineering, Aichi Institute of Technology
04/2021 - Current: Associate Professor, Department of Electrical and Electronics Engineering, Faculty of Engineering, Aichi Institute of Technology

Postal: 1247 Yachigusa, Yakusa-cho, Toyota, Aichi 470-0392, JAPAN
E-Mail: nfujieda at aitech dot ac.jp
Tel / Fax: +81-565-48-8121 (2103)