FTAC 2024

Abstract

This workshop aims to discuss novel ideas and methodologies of FPGA technologies for adaptive computing. As High-Performance Computing (HPC) and Artificial Intelligence (AI) technologies become more and more important, the needs for highly efficient computing systems and architectures have also been increasing. FPGA technologies are one of the promising schemes for highly efficient adaptive computing systems, where a specific computation is done by hardware accelerators, with a much shorter time and much smaller energy consumption.

Topics of interest

Topics of interests of this special session include, but are not limited to:

• FPGA acceleration for HPC applications, such as machine learning, data engineering, scientific computation, etc.
• Innovative FPGA technologies
• Interconnection network and network-on-chip for adaptive computing
• Optimized soft processors and processing elements on FPGA
• Rapid-prototyping for FPGA-based computing engines
• Asynchronous computing circuits on FPGA
• Tools for synthesizing custom computing circuits for FPGA
• Educational systems for experiencing FPGA acceleration

Proceedings

Download (Authorization is required: username and password will be shown in the workshop)

Invited Talk

1. Networking low-cost FPGA SoC-based SDR radar stations for coastal area observation

Yasunori Osana (Associate Professor, Kumamoto University)

Abstract

Conventionally, measurement devices such as buoys and ultrasonic wave height monitors have been used to measure ocean currents and waves in coastal areas. Although these devices can accurately measure conditions at the location where they are installed, they can only measure values at that point, making it difficult to cover large ocean areas. Additionally, maintenance costs are extremely high since they are installed on the ocean or the seabed.

On the other hand, using land-based facilities, HF ocean radar can measure ocean currents in vast ocean areas up to about 100 km away in near real-time. In North America, wide-area HF ocean radar networks are already in place to cover the continent's west and east coastlines. Still, commercial HF ocean radar equipment is expensive, and in Japan, the radars are only operated in a few locations within the country.

Over the past three years, our research group has developed and operated several HF ocean radar transceivers using SDR technology on FPGA SoCs. Based on the know-how gained through this project, we are currently developing a small and low-cost radar using relatively small-scale FPGA SoCs. Lower costs enable constructing a wide-area observation network that can be applied in various fields, including fisheries, maritime transportation, and weather forecasting.

In this talk, we will discuss the architecture and operation of a radar transceiver using FPGA and data obtained from observations at our radar stations.

2. Sparse-Sparse Matrix Multiplication Accelerator on FPGA featuring Distribute-Merge Product Dataflow

Thiem Van Chu (Assistant Professor, Tokyo Institute of Technology)

Abstract

Sparse-sparse matrix multiplication (SpMSpM) is a critical computational kernel that is widely used in various fields such as computational science and graph analysis. It poses computational challenges for general-purpose CPUs and GPUs due to its requirements for random memory access and the inherently low spatial/temporal locality. Given the significance of SpMSpM, numerous accelerators have been proposed recently. However, these accelerators suffer from various issues, including low input utilization, heavy computational load, and excessive memory traffic, particularly during the merging of intermediate results.

In this talk, I will present our recent work on a novel SpMSpM dataflow and introduce a high-performance, highly efficient accelerator architecture that leverages this new dataflow.

Program

Opening

Time: 13:00 - 13:10

Session 1: Invited Talk 1

Time: 13:10 - 13:50, Chair: Naoki Fujieda (Aichi Institute of Technology)

• Networking low-cost FPGA SoC-based SDR radar stations for coastal area observation, Yasunori Osana (Kumamoto University)

Session 2: Design and Implementation

Time: 13:55 - 15:15, Chair: Yasutaka Wada(Meisei University)

• A RISC-V Superscalar Processor Optimized for FPGA to Achieve High Operating Frequency, Noriaki Shimooka, Nesrine Berjab, Tomohiro Yoneda, and Kenji Kise (Tokyo Institute of Technology)
• Showing the Advantage of C2RTL by Comparing the Simulation Time with Verilog HDL in a RISC-V Processor Model, Yuta Takayasu, Yuji Yamada, Noriaki Shimooka, Nesrine Berjab, and Kenji Kise (Tokyo Institute of Technology)
• AXI Slave Interface for Communications Between Synchronous and Asynchronous Circuits, Shogo Semba and Hiroshi Saito (The University of Aizu)
• Accelerating Deep Learning Inference with Multiple FPGAs, Takumi Suzuki, Ryohei Kobayashi, Norihisa Fujita, and Taisuke Boku (University of Tsukuba)

Coffee Break

Time: 15:15 - 15:40

Session 3: Invited Talk 2

Time: 15:40 - 16:20, Chair: Ryohei Kobayashi (University of Tsukuba)

• Sparse-Sparse Matrix Multiplication Accelerator on FPGA featuring Distribute-Merge Product Dataflow, Thiem Van Chu (Tokyo Insitute of Technology)

Session 4: Network

Time: 16:25 - 17:25, Chair: Nesrine Berjab (Tokyo Institute of Technology)

• Towards a Resource-efficient Network Offload Engine for FPGAs using eBPF/XDP, Yuji Yamada and Kenji Kise (Tokyo Institute of Technology)
• ACiS: Complex Processing in the Switch Fabric, Pouya Haghi (University of Rochester), Anqi Guo (Boston University), Tong Geng (University of Rochester), Anthony Skjellum (Tennessee Tech), and Martin Herbordt (Boston University)
• Preliminary Evaluation of Flow Control on the Inter-FPGA Communication Framework CIRCUS, Kaito Kitazume, Norihisa Fujita, Ryohei Kobayashi, and Taisuke Boku (University of Tsukuba)

Submission Information

The submission of the extended abstract for this workshop has been closed.

Potential authors of this workshop should prepare the extended abstract of their paper, whose length is two (2) or three (3) pages. Each submitted extended abstract will be reviewed by at least three reviewers and will be evaluated based on usefulness, originality, relevance to the workshop's theme, and technical quality.

An extended abstract should be formatted in the same format as ICS 2024. See the submission guidelines of the ICS main conferencefor details (including the LaTeX template). However, submissions will be reviewed by the FTAC program committee through a single-blind process. This means that authors do not have to omit author names, affiliations, etc.

If authors get their extended abstract accepted, they have to submit the camera-ready version of their paper that is no longer than eight (8) pages. Also, at least one of the authors has to register for the conference, and an author has to present their paper at the workshop.

To encourage discussions on innovative ideas and methodologies of early stages, the proceedings of this workshop will only provided to the workshop attendees and will NOT published.

This workshop uses EasyChair to manage the submitted papers. To submit your extended abstract, please register the necessary information and upload your PDF at the submission page.

Important Dates

• Extended abstract submission: 23:59 JST (14:59 UTC), April 7, 2024
• Author notification: April 23, 2024
• Camera-ready submission: May 17, 2024 May 24, 2024
• Date of workshop: June 4, 2024

Committee

Organizing Committee

• General Chair: FUJIEDA, Naoki (Aichi Institute of Technology)
• Program Chair: SATO, Shimpei (Shinshu University)

Program Committee

• Program Chair: SATO, Shimpei (Shinshu University)
• KOBAYASHI, Ryohei (University of Tsukuba)
• KISE, Kenji (Tokyo Institute of Technology)
• MIYAJIMA, Takaaki (Meiji University)
• MIYOSHI, Takefumi (WasaLabo, LLC.)
• Nesrine Berjab (Tokyo Institute of Technology)
• OHKAWA, Takeshi (Kumamoto University)
• SAITO, Hiroshi (University of Aizu)
• TANAKA, Kiyofumi (JAIST)
• Thiem Van Chu (Tokyo Institute of Technology)
• WADA, Yasutaka (Meisei University)