VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity IO is
Port ( Pulse_IN : in std_logic_vector(15 downto 0);
Pulse_OUT : out std_logic_vector(31 downto 0);
Out_Select : in std_logic;
Dummy_IN5V :in std_logic_vector(4 downto 0);
Dummy_OUT : out std_logic);
end IO;
architecture RTL of IO is
begin
process (Pulse_IN, Out_Select) begin
if (Out_Select='0') then
Pulse_OUT <= "0000000000000000" & Pulse_IN;
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